This invention relates to the field of data processing systems. More particularly, this invention relates to branch target address caches for use within data processing systems.
It is known to provide branch target address caches coupled to prefetch circuitry within data processing systems to identify branch instructions early in the instruction pipeline and redirect instruction prefetching to predicted branch targets for those branch instructions. Known branch target address caches store the addresses of previously encountered branch instructions together with the target addresses for those previously encountered branch instructions. Accordingly, when a program instruction is fetched from a memory address matching a memory address stored within the branch target address cache from which a branch instruction has been previously fetched, then data identifying the branch target address can be read from the branch target address cache and used to redirect prefetching operations to the branch target.
In order to increase the effectiveness of a branch target address cache, it is desirable that it should have capacity to store data relating to a large number of previously encountered branch instructions. However, while providing a greater storage capacity to the branch target address cache increases the effectiveness with which it may identify previously encountered branch instructions, it has the disadvantage of increasing the amount of circuit overhead in terms of area and power consumption that is associated with the maintenance and operation of the branch target address cache.